Element substrate and light emitting device

ABSTRACT

A light emitting device and an element substrate which are capable of suppressing variations in the luminance intensity of a light emitting element among pixels due to characteristic variations of a driving transistor without suppressing off-current of a switching transistor low and increasing storage capacity of a capacitor. According to the invention, a depletion mode transistor is used as a driving transistor. The gate of the driving transistor is fixed in its potential or connected to the source or drain thereof to operate in a saturation region with a constant current flow. A current controlling transistor which operates in a linear region is connected in series to the driving transistor, and a video signal for transmitting a light emission or non-emission of a pixel is inputted to the gate of the current controlling transistor through a switching transistor.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.13/804,538, filed Mar. 14, 2013, now allowed, which is a continuation ofU.S. application Ser. No. 13/480,550, filed May 25, 2012, now U.S. Pat.No. 8,400,067, which is a continuation of U.S. application Ser. No.13/184,616, filed Jul. 18, 2011, now U.S. Pat. No. 8,212,488, which is acontinuation of U.S. application Ser. No. 11/562,626, filed Nov. 22,2006, now U.S. Pat. No. 8,004,200, which is a divisional of U.S.application Ser. No. 10/799,857, filed Mar. 15, 2004, now U.S. Pat. No.7,141,934, which claims the benefit of foreign priority applicationsfiled in Japan as Serial No. 2003-086496 on Mar. 26, 2003, and SerialNo. 2003-139554 on May 16, 2003, all of which are incorporated byreference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a light emitting device comprising aplurality of pixels each having a light emitting element and a means forsupplying current to the light emitting element.

2. Description of the Related Art

Since a light emitting element emits light by itself, it is highlyvisible and does not require a back light which is needed in a liquidcrystal display device (LCD). Therefore, it is suitably applied to thindevices and not restricted in viewing angle. Because of theseadvantages, a light emitting device having a light emitting element hasrecently been drawing attentions as an alternative display device to aCRT and an LCD. It is to be noted that a light emitting element in thisspecification indicates an element whose luminance is controlled bycurrent or voltage, and it includes an OLED (Organic Light EmittingDiode) or an MIM electron source element (electron discharge element)and the like which is used in an FED (Field Emission Display).

Also, a light emitting device of the invention includes a panel and amodule obtained by mounting an IC or the like onto the panel. Moregenerally, the invention relates to an element substrate whichcorresponds to the one before the completion of a panel in manufacturingsteps of the light emitting device, and the element substrate comprisesa plurality of pixels each having a means for supplying current to alight emitting element.

OLED which is one of the light emitting elements includes an anodelayer, a cathode layer, and a layer containing an electric field lightemitting material (hereinafter referred to as an electroluminescentlayer) that generates luminescence (electroluminescence) when anelectric field is applied thereto. The electroluminescent layer isprovided between an anode and cathode, and it comprises a single ormultiple layers. These layers may contain an inorganic compound. Theelectroluminescence in the electroluminescent layer includes a lightemission (fluorescence) when a singlet exciting state returns to aground state and a light emission (phosphorescence) when a tripletexciting state returns to a ground state.

Next, the configuration of a pixel of a general light emitting deviceand its drive will be described in brief. A pixel shown in FIG. 9comprises a switching transistor 900, a driving transistor 901, acapacitor 902, and a light emitting element 903. The gate of theswitching transistor 900 is connected to a scan line 905. Either thesource or drain of the switching transistor 900 is connected to a signalline 904, and the other is connected to the gate of the drivingtransistor 901. The source of the driving transistor 901 is connected toa power supply line 906, and the drain of the driving transistor 901 isconnected to the anode of the light emitting element 903. The cathode ofthe light emitting element 903 is connected to a counter electrode 907.The capacitor 902 is provided for storing a potential difference betweenthe gate and source of the driving transistor 901. Also, thepredetermined voltages are applied to the power supply line 906 and thecounter electrode 907 from a power supply and each has a potentialdifference.

When the switching transistor 900 is turned ON by a signal from the scanline 905, a video signal that is inputted to the signal line 904 isinputted to the gate of the driving transistor 901. The potentialdifference between a potential of the inputted video signal and that ofthe power supply line 906 corresponds to a gate-source voltage Vgs ofthe driving transistor 901. Thus, current is supplied to the lightemitting element 903, and the light emitting element 903 emits light byusing the supplied current.

SUMMARY OF THE INVENTION

A transistor using polysilicon has high field effect mobility and largeon-current. Therefore, it is suited for a light emitting device.However, the transistor using polysilicon has problems in that it islikely to have variations in characteristics due to a defect in acrystal grain boundary.

In the pixel shown in FIG. 9, when the magnitude of the drain current ofthe driving transistor 901 differs among pixels, the luminance intensityof the light emitting element 903 varies even with the same potential ofa video signal.

As a means for controlling variations in drain current, there is amethod for enlarging an L/W (L: channel length, W: channel width) of thedriving transistor 901 as disclosed in Japanese Patent Application No.2003-008719. The drain current Ids of the driving transistor 901 in asaturation region is expressed by the following formula 1.

Ids=â(Vgs−Vth)²/2   (formula 1)

It is apparent from the formula 1 that, the drain current Ids in thesaturation region of the driving transistor 901 is easily fluctuatedeven by small variations in the gate-source voltage Vgs. Therefore, itis necessary to keep the gate-source voltage Vgs, which is storedbetween the gate and source of the driving transistor 901, not to bevaried while the light emitting element 901 emits light. Thus, storagecapacity of the capacitor 902 which is disposed between the gate andsource of the driving transistor 901 is required to be increased, andoff-current of the switching transistor 900 is required to be suppressedlow.

It is quite difficult to suppress off-current of the switchingtransistor 900 low, to increase on-current thereof for charging largecapacitance, and to achieve both of them in the formation process of thetransistor.

Also, there is another problem that the gate-source voltage Vgs of thedriving transistor 901 is varied due to the switching of the switchingtransistor 900, and potential changes in the signal line, scan line, andthe like. This derives from the parasitic capacitance on the gate of thedriving transistor 901.

In view of the foregoing problems, the invention provides a lightemitting device and an element substrate which are not easily influencedby parasitic capacitance and capable of suppressing variations inluminance intensity of the light emitting element 903 among pixels dueto characteristic variations of the driving transistor 901 withoutsuppressing off-current of the switching transistor 900 low andincreasing storage capacity of the capacitor 902.

According to the invention, a depletion mode transistor is used as adriving transistor. The gate of the driving transistor is fixed in itspotential or connected to the source or drain thereof to operate in asaturation region with a constant current flow. Also, a currentcontrolling transistor which operates in a linear region is connected inseries to the driving transistor. A video signal for transmitting alight emission or non-emission of a pixel is inputted to the gate of thecurrent controlling transistor through a switching transistor.

Transistors other than the driving transistor are normal enhancementmode transistors here.

Since the current controlling transistor operates in a linear region,its source-drain voltage Vds is small, and small changes in agate-source voltage Vgs of the current controlling transistor do notinfluence the current flowing in a light emitting element. Currentflowing in the light emitting element is determined by the drivingtransistor which operates in a saturation region.

Current flowing in the light emitting element is not influenced evenwithout increasing storage capacity of a capacitor which is disposedbetween the gate and source of the current controlling transistor orsuppressing off-current of the switching transistor low. In addition, itis not influenced by the parasitic capacitance on the gate of thecurrent controlling transistor either. Therefore, cause of variation isdecreased, and image quality is thus enhanced to a great extent.

In addition, as there is no need to suppress off-current of theswitching transistor low, manufacturing process of the transistor can besimplified, thus contributes greatly to the cost reduction andimprovement in yield.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing an embodiment mode of the invention.

FIG. 2 is a diagram showing an embodiment mode of the invention.

FIG. 3 is a diagram showing an embodiment mode of the invention.

FIG. 4 is a diagram showing an embodiment mode of the invention.

FIG. 5 is a schematic view showing an external circuit and a panel.

FIG. 6 is a diagram showing the configuration example of a signal drivercircuit.

FIG. 7 is an example showing a top plan view of the invention.

FIGS. 8A to 8D are examples showing electronic apparatuses to which theinvention is applied.

FIG. 9 is a diagram of an embodiment.

FIG. 10 is an example showing a top plan view of the invention.

FIGS. 11A and 11B are examples showing cross-sectional structures of theinvention.

FIG. 12 is an example showing the operation timing of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiment modes of the invention are described in detail with referenceto the accompanying drawings below.

Embodiment Mode 1

FIG. 1 shows an embodiment mode of a pixel of the light emitting deviceof the invention. The pixel shown in FIG. 1 comprises a light emittingelement 104, a transistor (switching transistor) 101 used as a switchingelement for controlling an input of a video signal to the pixel, adriving transistor 102 for controlling current flowing in the lightemitting element 104, and a current controlling transistor 103 forcontrolling a current supply to the light emitting element 104. Inaddition, it is also possible to dispose in the pixel a capacitor 105for storing a potential of a video signal.

The driving transistor 102 and the current controlling transistor 103have the same conductivity. It is assumed that the driving transistor102 is a depletion mode transistor, and the rest of the transistors arenormal enhancement mode transistors. In the invention, the drivingtransistor 102 is operated in a saturation region and the currentcontrolling transistor 103 is operated in a linear region.

The channel length (L) of the driving transistor 102 may be longer thanits channel width (W), and L of the current controlling transistor 103may be equal to or shorter than its W. Desirably, the ratio of L to W(L/W) of the driving transistor 102 is five or more.

The gate of the switching transistor 101 is connected to a scan line Gj(j=1 to y). Either the source or drain of the switching transistor 101is connected to a signal line Si (i=1 to x), and the other is connectedto the gate of the current controlling transistor 103. The gate of thedriving transistor 102 is connected to a power supply line Vi (i=1 tox). The driving transistor 102 and the current controlling transistor103 are each connected to the power supply line Vi (i=1 to x) and thelight emitting element 104 so that a current supplied from the powersupply line Vi (i=1 to x) is supplied to the light emitting element 104as a drain current of the driving transistor 102 and of the currentcontrolling transistor 103. In this embodiment mode, the source of thecurrent controlling transistor 103 is connected to the power supply lineVi (i=1 to x) and the drain of the driving transistor 102 is connectedto a pixel electrode of the light emitting element 104.

It is to be noted that the source of the driving transistor 102 may beconnected to the power supply line Vi (i=1 to x), and the drain of thecurrent controlling transistor 103 may be connected to the pixelelectrode of the light emitting element 104.

The light emitting element 104 comprises an anode, a cathode, and alight emitting layer interposed between the anode and cathode. As shownin FIG. 1, when the anode of the light emitting element 104 is connectedto the driving transistor 102, the anode is a pixel electrode and thecathode is a counter electrode. The counter electrode of the lightemitting element 104 and the power supply line Vi (i=1 to x) are made tohave a potential difference so that current flows into the lightemitting element 104 in the forward bias direction.

One of the two electrodes of the capacitor 105 is connected to the powersupply line Vi (i=1 to x), and the other is connected to the gate of thecurrent controlling transistor 103. The capacitor 105 is disposed so asto store a potential difference between the two electrodes of thecapacitor 105 when the switching transistor 101 is not selected (offstate). It is to be noted that although FIG. 1 shows a configurationdisposing the capacitor 105, the invention is not limited to this and analternative configuration without the capacitor 105 may be employed aswell.

In FIG. 1, each of the driving transistor 102 and the currentcontrolling transistor 103 is a P-type transistor, and the drain of thedriving transistor 102 is connected to the anode of the light emittingelement 104. On the contrary, in the case where each of the drivingtransistor 102 and the current controlling transistor 103 is an N-typetransistor, the source of the driving transistor 102 is connected to thecathode of the light emitting element 104. In this case, the cathode ofthe light emitting element 104 is a pixel electrode and the anodethereof is a counter electrode.

Next, a driving method of the pixel shown in FIG. 1 is described. Theoperation of the pixel shown in FIG. 1 can be divided into a writingperiod and a data storage period. First, in the writing period, when thescan line Gj (j=1 to y) is selected, the switching transistor 101 whosegate is connected to the scan line Gj (j=1 to y) is turned ON. Then, avideo signal which is inputted to the signal line Si (i=1 to x) isinputted to the gate of the current controlling transistor 103 throughthe switching transistor 101. The driving transistor 102 is ON at alltimes as its gate is connected to the power supply line Vi (i=1 to x).

When the current controlling transistor 103 is turned ON by a videosignal, current is supplied to the light emitting element 104 throughthe current supply line Vi (i=1 to x). At this time, the currentcontrolling transistor 103 operates in a linear region, thus currentflowing in the light emitting element 104 is determined by volt-amperecharacteristics of the driving transistor 102 operating in a saturationregion and the light emitting element 104. The light emitting element104 emits light at luminance corresponding to the magnitude of thesupplied current.

Meanwhile, when the current controlling transistor 103 is turned OFF bya video signal, no current is supplied to the light emitting element104, thus it does not emit light. It is to be noted that according tothe invention, it is possible to control current not to be supplied tothe light emitting element 104 even when the driving transistor 102 is adepletion mode transistor since the current controlling transistor 103is an enhancement mode transistor.

In the data storage period, the switching transistor 101 is turned OFFby controlling a potential of the scan line Gj (j=1 to y), therebystoring a potential of the video signal that is written in the writingperiod. In the writing period, when the current controlling transistor103 is turned ON, a potential of a video signal is stored in thecapacitor 105, therefore, the current supply to the light emittingelement 104 is kept on. On the contrary, when the current controllingtransistor 103 is turned OFF in the writing period, a potential of avideo signal is stored in the capacitor 105, therefore, current is notsupplied to the light emitting element 104.

An element substrate of the invention corresponds to the one before theformation of a light emitting element in manufacturing steps of thelight emitting device of the invention.

A transistor used in the light emitting device of the invention may be atransistor formed by using single crystalline silicon or an SOI, a thinfilm transistor using polycrystalline silicon or amorphous silicon, or atransistor using an organic semiconductor or a carbon nanotube. Inaddition, a transistor disposed in a pixel of the light emitting deviceof the invention may be a single gate transistor, a double gatetransistor, or a multi-gate transistor having more than two gateelectrodes.

According to the above-described configuration, a source-drain voltageVds of the current controlling transistor 103 is small as the currentcontrolling transistor 103 operates in a linear region, therefore, smallchanges in the gate-source voltage Vgs of the current controllingtransistor 103 do not influence the current flowing in a light emittingelement 104. Current flowing in the light emitting element 104 isdetermined by the driving transistor 102 which operates in a saturationregion. Current flowing in the light emitting element 104 is notinfluenced even without increasing storage capacity of the capacitor 105which is disposed between the gate and source of the current controllingtransistor 103 or suppressing off-current of the switching transistor101 low. In addition, it is not influenced by the parasitic capacitanceon the gate of the current controlling transistor 103 either. Therefore,cause of variation is decreased, and image quality is thus enhanced to agreat extent.

Embodiment Mode 2

Described in this embodiment mode is a different configuration of apixel of the light emitting device from that shown in FIG. 1.

The pixel shown in FIG. 2 comprises a light emitting element 204, aswitching transistor 201, a driving transistor 202, a currentcontrolling transistor 203, and a transistor (erasing transistor) 206for turning OFF the current controlling transistor 203 forcibly. Inaddition, it is also possible to dispose a capacitor 205 in addition tothe aforementioned elements.

The driving transistor 202 and the current controlling transistor 203have the same conductivity. The size, characteristics, and operatingregion of each transistor may be set in the same manner as EmbodimentMode 1.

The gate of the switching transistor 201 is connected to a first scanline Gaj (j=1 to y). Either the source or drain of the switchingtransistor 201 is connected to a signal line Si (i=1 to x), and theother is connected to the gate of the current controlling transistor203. The gate of the erasing transistor 206 is connected to a secondscan line Gej (j=1 to y). Either the source or drain of the erasingtransistor 206 is connected to a power supply line Vi (i=1 to x), andthe other is connected to the gate of the current controlling transistor203. The gate of the driving transistor 202 is connected to the powersupply line Vi (i=1 to x). The driving transistor 202 and the currentcontrolling transistor 203 are each connected to the power supply lineVi (i=1 to x) and the light emitting element 204 so that a currentsupplied from the power supply line Vi (i=1 to x) is supplied to thelight emitting element 204 as a drain current of the driving transistor202 and of the current controlling transistor 203. In this embodimentmode, the source of the current controlling transistor 203 is connectedto the power supply line Vi (i=1 to x) and the drain of the drivingtransistor 202 is connected to a pixel electrode of the light emittingelement 204.

It is to be noted that the source of the driving transistor 202 may beconnected to the power supply line Vi (i=1 to x), and the drain of thecurrent controlling transistor 203 may be connected to the pixelelectrode of the light emitting element 204.

The light emitting element 204 comprises an anode, a cathode, and alight emitting layer interposed between the anode and cathode. As shownin FIG. 2, when the anode of the light emitting element 204 is connectedto the driving transistor 202, the anode is a pixel electrode and thecathode is a counter electrode. The counter electrode of the lightemitting element 204 and the power supply line Vi (i=1 to x) have apotential difference so that current flows into the light emittingelement 204 in the forward bias direction.

One of the two electrodes of the capacitor 205 is connected to the powersupply line Vi (i=1 to x), and the other is connected to the gate of thecurrent controlling transistor 203.

In FIG. 2, each of the driving transistor 202 and the currentcontrolling transistor 203 is a P-type transistor, and the drain of thedriving transistor 202 is connected to the anode of the light emittingelement 204. On the contrary, in the case where each of the drivingtransistor 202 and the current controlling transistor 203 is an N-typetransistor, the source of the driving transistor 202 is connected to thecathode of the light emitting element 204. In this case, the cathode ofthe light emitting element 204 is a pixel electrode and the anodethereof is a counter electrode.

The operation of the pixel shown in FIG. 2 can be divided into a writingperiod, a data storage period, and an erasing period. The operations ofthe switching transistor 201, the driving transistor 202, and thecurrent controlling transistor 203 in writing period and data storageperiod are the same as those in FIG. 1.

In erasing period, the second scan line Gej (j=1 to y) is selected toturn ON the erasing transistor 206, thus a potential of the power supplyline Vi (i=1 to x) is supplied to the gate of the current controllingtransistor 203 through the erasing transistor 206. Therefore, thecurrent controlling transistor 203 is turned OFF, and the light emittingelement 204 can be forcibly brought into the state where no current issupplied.

Embodiment Mode 3

Described in this embodiment mode is a different configuration of apixel of the light emitting device of the invention from those ofEmbodiment Modes 1 and 2.

The pixel shown in FIG. 3 comprises a light emitting element 304, atransistor (switching transistor) 301 used as a switching element forcontrolling input of a video signal to the pixel, a driving transistor302 for controlling a current flowing into the light emitting element304, a current controlling transistor 303 for controlling a currentsupply to the light emitting element 304. In addition, it is alsopossible to dispose a capacitor 305 for storing a potential of a videosignal as shown in the figure.

The driving transistor 302 and the current controlling transistor 303have the same conductivity. The size, characteristics, and operatingregion of each transistor may be set in the same manner as those ofEmbodiment Mode 1.

The gate of the switching transistor 301 is connected to a scan line Gj(j=1 to y). Either the source or drain of the switching transistor 301is connected to a signal line Si (i=1 to x), and the other is connectedto the gate of the current controlling transistor 303. The gate of thedriving transistor 302 is connected to the source thereof. The drivingtransistor 302 and the current controlling transistor 303 are eachconnected to a power supply line Vi (i=1 to x) and the light emittingelement 304 so that a current supplied from the power supply line Vi(i=1 to x) is supplied to the light emitting element 304 as a draincurrent of the driving transistor 302 and of the current controllingtransistor 303. In this embodiment mode, the source of the currentcontrolling transistor 303 is connected to the power supply line Vi (i=1to x) and the drain of the driving transistor 302 is connected to apixel electrode of the light emitting element 304.

It is to be noted that the source and gate of the driving transistor 302may be connected to the power supply line Vi (i=1 to x), and the drainof the current controlling transistor 303 may be connected to the pixelelectrode of the light emitting element 304.

The light emitting element 304 comprises an anode, a cathode, and alight emitting layer interposed between the anode and cathode. As shownin FIG. 3, when the anode of the light emitting element 304 is connectedto the driving transistor 302, the anode is a pixel electrode and thecathode is a counter electrode. The counter electrode of the lightemitting element 304 and the power supply line Vi (i=1 to x) have apotential difference so that current flows into the light emittingelement 304 in the forward bias direction.

One of the two electrodes of the capacitor 305 is connected to the powersupply line Vi (i=1 to x), and the other is connected to the gate of thecurrent controlling transistor 303. The capacitor 305 is disposed so asto store a potential difference between the two electrodes of thecapacitor 305 when the switching transistor 301 is not selected (offstate). It is to be noted that although FIG. 3 shows a configurationdisposing the capacitor 305, the invention is not limited to this and analternative configuration without the capacitor 305 may be employed aswell.

In FIG. 3, each of the driving transistor 302 and the currentcontrolling transistor 303 is a P-type transistor, and the drain of thedriving transistor 302 is connected to the anode of the light emittingelement 304. On the contrary, in the case where each of the drivingtransistor 302 and the current controlling transistor 303 is an N-typetransistor, the source of the driving transistor 302 is connected to thecathode of the light emitting element 304. In this case, the cathode ofthe light emitting element 304 is a pixel electrode and the anodethereof is a counter electrode.

The operation of the pixel shown in FIG. 3 is the same as that shown inFIG. 1.

Embodiment Mode 4

Described in this embodiment mode is a different configuration of apixel of the light emitting device of the invention from those ofEmbodiment Modes 1 to 3.

The pixel shown in FIG. 4 comprises a light emitting element 404, aswitching transistor 401, a driving transistor 402, a currentcontrolling transistor 403, and a transistor (erasing transistor) 406for erasing a potential of a written video signal. It is also possibleto dispose a capacitor 405 in addition to the above elements.

The driving transistor 402 and the current controlling transistor 403have the same conductivity. The size, characteristics, and operatingregion of each transistor may be set in the same manner as those ofEmbodiment Mode 1.

The gate of the switching transistor 401 is connected to a first scanline Gaj (j=1 to y). Either the source or drain of the switchingtransistor 401 is connected to a signal line Si (i=1 to x), and theother is connected to the gate of the current controlling transistor403. The gate of the erasing transistor 406 is connected to a secondscan line Gej (j=1 to y). Either the source or drain of the erasingtransistor 406 is connected to a second scan line Gej (i=1 to x), andthe other is connected to the gate of the current controlling transistor403. The gate of the driving transistor 402 is connected to the sourcethereof. The driving transistor 402 and the current controllingtransistor 403 are each connected to a power supply line Vi (i=1 to x)and the light emitting element 404 so that a current supplied from thepower supply line Vi (i=1 to x) is supplied to the light emittingelement 404 as a drain current of the driving transistor 402 and of thecurrent controlling transistor 403. In this embodiment mode, the sourceof the current controlling transistor 403 is connected to the powersupply line Vi (i=1 to x) and the drain of the driving transistor 402 isconnected to a pixel electrode of the light emitting element 404.

It is to be noted that the source of the driving transistor 402 may beconnected to the power supply line Vi (i=1 to x), and the drain of thecurrent controlling transistor 403 may be connected to the pixelelectrode of the light emitting element 404.

The light emitting element 404 comprises an anode, a cathode, and alight emitting layer interposed between the anode and cathode. As shownin FIG. 4, when the anode of the light emitting element 404 is connectedto the driving transistor 402, the anode is a pixel electrode and thecathode is a counter electrode. The counter electrode of the lightemitting element 404 and the power supply line Vi (i=1 to x) have apotential difference so that current flows into the light emittingelement 404 in the forward bias direction.

One of the two electrodes of the capacitor 405 is connected to the powersupply line Vi (i=1 to x), and the other is connected to the gate of thecurrent controlling transistor 403.

In FIG. 4, each of the driving transistor 402 and the currentcontrolling transistor 403 is a P-type transistor, and the drain of thedriving transistor 402 is connected to the anode of the light emittingelement 404. On the contrary, in the case where each of the drivingtransistor 402 and the current controlling transistor 403 is an N-typetransistor, the source of the driving transistor 402 is connected to thecathode of the light emitting element 404. In this case, the cathode ofthe light emitting element 404 is a pixel electrode and the anodethereof is a counter electrode.

The operation of the pixel shown in FIG. 4 is the same as that shown inFIG. 2.

In addition, either an N-type transistor or a P-type transistor may beemployed as a switching transistor and an erasing transistor used in theinvention.

Embodiment 1

Described in this embodiment are a configuration of an active matrixdisplay device to which the pixel configuration of the invention isapplied and its drive.

FIG. 5 shows a block diagram of an external circuit and a schematic viewof a panel.

An active matrix display device shown in FIG. 5 comprises an externalcircuit 5004 and a panel 5010. The external circuit 5004 comprises anA/D converter unit 5001, a power supply unit 5002, and a signalgenerator unit 5003. The A/D converter unit 5001 converts an image datasignal which is inputted as an analog signal into a digital signal(video signal), and supplies it to a signal driver circuit 5006. Thepower supply unit 5002 generates power having a predetermined voltagefrom the power supplied from a battery or an outlet, and supplies it tothe signal driver circuit 5006, scan driver circuits 5007, an OLED 5011,the signal generator unit 5003, and the like. The signal generator unit5003 is inputted with power, an image signal, a synchronizing signal,and the like. Also, it generates a clock signal and the like for drivingthe signal driver circuit 5006 and the scan driver circuits 5007.

A signal and power from the external circuit 5004 are inputted to aninternal circuit and the like through an FPC and an FPC connectionportion 5005 in the panel 5010.

The pixel 5010 comprises a substrate 5008 mounting the FPC connectionportion 5005, the internal circuit, and the OLED 5011. The internalcircuit comprises the signal driver circuit 5006, the scan drivercircuits 5007, a pixel portion 5009. Although FIG. 5 employs the pixelshown in Embodiment Mode 1, an alternative pixel configuration shown inother embodiment modes of the invention may be employed as well.

The pixel portion 5009 is disposed in the center of the substrate, andthe signal driver circuit 5006 and the scan driver circuit 5007 aredisposed on the periphery of the pixel portion 5009. The OLED 5011 and acounter electrode of the OLED are formed over the pixel portion 5009.

FIG. 6 shows a more detailed block diagram of the signal driver circuit5006.

The signal driver circuit 5006 comprises a shift register 6002 includinga plurality of stages of D-flip flops 6001, a data latch circuit 6003, alatch circuit 6004, a level shifter 6005, a buffer 6006, and the like.

It is assumed that a clock signal (S-CK), an inverted clock signal(S-CKB), a start pulse (S-SP), a video signal (DATA), and a latch pulse(LatchPulse) are inputted.

First, in accordance with a clock signal, an inverted clock signal, anda start pulse, a sampling pulse is sequentially outputted from the shiftregister 6002. In accordance with the timing in which the sampling pulseis inputted to the data latch circuit 6003, a video signal is sampledand thus stored. This operation is sequentially performed from the firstcolumn.

When the storage of a video signal is completed in the data latchcircuit 6003 on the last stage, a latch pulse is inputted during ahorizontal retrace period, and the video signal stored in the data latchcircuit 6003 is transferred to the latch circuit 6004 all at once. Then,it is level-shifted in the level shifter 6005, and adjusted in thebuffer 6006 so as to be outputted to signal lines S1 to Sn all at once.At this time, an H-level or an L-level signal is inputted to pixels inthe row selected by the scan driver circuits 5007, thereby controlling alight emission or non-emission of the OLED 5011.

Although the active matrix display device shown in this embodimentcomprises the panel 5010 and the external circuit 5004 each formedindependently, they may be integrally formed on the same substrate.Also, although the display device employs OLED in this embodiment, otherlight emitting elements can be employed as well. In addition, the levelshifter 6005 and the buffer 6006 may not necessarily be provided in thesignal driver circuit 5006.

Embodiment 2

Described in this embodiment is a top plan view of the pixel shown inFIG. 2. FIG. 7 shows a top plan view of a pixel of this embodiment.

Reference numeral 7001 denotes a signal line, 7002 denotes a powersupply line, 7004 denotes a first scan line, and 7003 denotes a secondscan line. In this embodiment, the signal line 7001 and the power supplyline 7002 are formed of the same conductive film, and the first scanline 7004 and the second scan line 7003 are formed of the sameconductive film. Reference numeral 7005 denotes a switching transistor,and a part of the first scan line 7004 functions as its gate electrode.Reference numeral 7006 denotes an erasing transistor, and a part of thesecond scan line 7003 functions as its gate electrode. Reference numeral7007 denotes a driving transistor, and 7008 denotes a currentcontrolling transistor. An active layer of the driving transistor 7007is curved so that its L/W becomes larger than that of the currentcontrolling transistor 7008. Reference numeral 7009 denotes a pixelelectrode, and light is emitted in its overlapped area (light emittingarea) 7010 with a light emitting layer and a cathode (neither of them isshown).

It is to be noted that the top plan view of the invention shown in thisembodiment is only an example, and the invention is, needless to say,not limited to this.

Embodiment 3

Described in this embodiment is an example of a top plan view of thepixel shown in FIG. 2, which is different from that shown in FIG. 7.FIG. 10 shows a top plan view of a pixel of this embodiment.

Reference numeral 10001 denotes a signal line, 10002 denotes a powersupply line, 10004 denotes a first scan line, and 10003 denotes a secondscan line. In this embodiment, the signal line 10001 and the powersupply line 10002 are formed of the same conductive film, and the firstscan line 10004 and the second scan line 10003 are formed of the sameconductive film. Reference numeral 10005 denotes a switching transistor,and a part of the first scan line 10004 functions as its gate electrode.Reference numeral 10006 denotes a erasing transistor, and a part of thesecond scan line 10003 functions as its gate electrode. Referencenumeral 10007 denotes a driving transistor, and 10008 denotes a currentcontrolling transistor. An active layer of the driving transistor 10007is curved so that its L/W becomes larger than that of the currentcontrolling transistor 10008. Reference numeral 10009 denotes a pixelelectrode, and light is emitted in its overlapped area (light emittingarea) 10010 with a light emitting layer and a cathode (neither of themis shown).

It is to be noted that the top plan view of this embodiment is only anexample, and the invention is, needless to say, not limited to this.

Embodiment 4

Described in this embodiment is a cross-sectional structure of a pixel.

FIG. 11A shows a cross-sectional view of a pixel in which a drivingtransistor 11021 is a P-type transistor and light emitted from a lightemitting element 11022 is transmitted to an anode side 11023. In FIG.11A, the anode 11023 of the light emitting element 11022 is electricallyconnected to the driving transistor 11021, and a light emitting layer11024 and a cathode 11025 are laminated on the anode 11023 in thisorder. As for the cathode 11025, known material can be used as long asit is a conductive film having a small work function and reflectinglight. For example, Ca, Al, CaF, MgAg, AlLi, and the like are desirablyused. The light emitting layer 11024 may comprise a single layer ormultiple layers. When it comprises multiple layers, a hole injectionlayer, a hole transporting layer, a light emitting layer, an electrontransporting layer, and an electron injection layer are sequentiallylaminated in this order on the cathode 11023. It is to be noted that notall of the above layers are necessarily provided. The anode 11023 may beformed of a transparent conductive film which transmits light, such asthe one comprising ITO or the one in which indium oxide is mixed withzinc oxide (ZnO) of 2 to 20%.

The overlapped portion of the anode 11023, the light emitting layer11024, and the cathode 11025 corresponds to the light emitting element11022. In the case of the pixel shown in FIG. 11A, light emitted fromthe light emitting element 11022 is transmitted to the anode 11023 sideas shown by an outline arrow.

FIG. 11B shows a cross-sectional view of a pixel in which a drivingtransistor 11001 is an N-type transistor and light emitted from a lightemitting element 11002 is transmitted to an anode side 11005. In FIG.11B, a cathode 11003 of the light emitting element 11002 is electricallyconnected to the driving transistor 11001, and a light emitting layer11004 and an anode 11005 are laminated on the cathode 11003 in thisorder. As for the cathode 11005, known material can be used as long asit is a conductive film having a small work function and reflectinglight. For example, Ca, Al, CaF, MgAg, AlLi, and the like are desirablyused. The light emitting layer 11004 may comprise a single layer ormultiple layers. When it comprises multiple layers, a hole injectionlayer, a hole transporting layer, a light emitting layer, an electrontransporting layer, and an electron injection layer are sequentiallylaminated in this order on the cathode 11003. It is to be noted that notall the above layers are necessarily provided. The anode 11005 may beformed of a transparent conductive film which transmits light, such asthe one comprising ITO or the one in which indium oxide is mixed withzinc oxide (ZnO) of 2 to 20%.

The overlapped portion of the anode 11003, the light emitting layer11004, and the cathode 11005 corresponds to the light emitting element11002. In the case of the pixel shown in FIG. 11B, light emitted fromthe light emitting element 11002 is transmitted to the anode 11003 sideas shown by an outline arrow.

It is to be noted that although shown in this embodiment is the one inwhich a driving transistor is electrically connected to a light emittingelement, a current controlling transistor may be interposed between thedriving transistor and the light emitting element.

Embodiment 5

Described in this embodiment is an example of the drive timing where thepixel configuration of Embodiment Mode 2 is employed.

FIG. 12A shows an example using a digital time gray scale method for a4-bit gray scale display. In data storage periods Ts1 to Ts4, the ratioof the time length is assumed to be Ts1:Ts2:Ts3:Ts4=2³:2²:2¹:2⁰=8:4:2:1.

The operation is described next. First, in a writing period Tb1, thefirst scan line is selected from the first row in sequence, therebyturning ON the switching transistor. Next, a video signal is inputted toeach pixel from a signal line, thereby controlling a light emission ornon-light emission of each pixel according to a potential of the signal.Once the video signal is written, that row proceeds to the data storageperiod Ts1 immediately. The same operation is performed up to the lastrow, and thus a period Ta1 terminates. Subsequently, a writing periodTb2 is started from the row in which the data storage period Ts1 iscomplete in sequence.

In the sub-frame period having the shorter data storage period than thewriting period (corresponds to a period Ta4 here), an erasing period2102 is provided so that a next writing period is not startedimmediately after the data storage period. In the erasing period, alight emitting element is forced to be in a non-emission state.

Taken as an example here is the case of expressing a 4-bit gray scaledisplay, however the number of bits and gray scales is not limited tothis. In addition, light emission is not necessarily performed from Ts1to Ts4 in sequence. It may be performed at random, or divided into aplurality of periods.

Embodiment 6

The display device of the invention can be used in display portions ofvarious electronic apparatuses. In particular, the display device of theinvention is desirably applied to a mobile device that requires lowpower consumption.

Electronic apparatuses using the display device of the invention includea portable information device (a cellular phone, a mobile computer, aportable game machine, an electronic book, and the like), a videocamera, a digital camera, a goggle display, a display device, anavigation system, and the like. Specific examples of these electronicapparatuses are shown in FIGS. 8A to 8D.

FIG. 8A shows a display device which includes a housing 8001, an audiooutput portion 8002, a display portion 8003, and the like. The displaydevice of the invention can be used for the display portion 8003. Notethat, the display device includes all the information display devicesfor personal computers, television broadcast reception, advertisementdisplays, and the like.

FIG. 8B shows a mobile computer which includes a main body 8101, astylus 8102, a display portion 8103, operation keys 8104, an externalinterface 8105, and the like. The display device of the invention can beused for the display portion 8103.

FIG. 8C shows a game machine which includes a main body 8201, a displayportion 8202, operation keys 8203, and the like. The display device ofthe invention can be used for the display portion 8202.

FIG. 8D shows a cellular phone which includes a main body 8301, an audiooutput portion 8302, a display portion 8304, operation switches 8305, anantenna 8306, and the like. The display device of the invention can beused for the display portion 8304.

As described above, an application range of the invention is so widethat the invention can be applied to electronic apparatuses in variousfields.

Although the invention has been fully described by way of example withreference to the accompanying drawings, it is to be understood thatvarious modifications will be apparent to those skilled in the art.Therefore, unless otherwise such changes and modifications depart fromthe scope of the invention hereinafter defined, they should beconstructed as being included therein.

1. (canceled)
 2. A light emitting device comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a first line; a second line; a third line; a fourth line; a fifth line; a sixth line; a capacitor; and a light emitting element, wherein: a channel formation region of the second transistor and a channel formation region of the fourth transistor are formed of a same semiconductor island; a channel formation region of the first transistor and a channel formation region of the third transistor are formed of a same semiconductor island; a conductivity type of the first transistor and a conductivity of the third transistor is the same; one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor; a gate of the first transistor is electrically connected to one electrode of the capacitor; the gate of the first transistor is electrically connected to one of a source and a drain of the fourth transistor through a metal layer; the gate of the first transistor is electrically connected to one of a source and a drain of the second transistor through the metal layer; the metal layer comprises a region that overlaps with a part of the second line; a gate of the second transistor is electrically connected to the second line; the third line comprises a region that overlaps with a part of the channel formation region of the first transistor; the other of the source and the drain of the third transistor is electrically connected to the light emitting element; the other of the source and the drain of the fourth transistor is electrically connected to the fourth line; a gate of the fourth transistor is electrically connected to the first line; the other electrode of the capacitor is electrically connected to the third line; the other electrode of the capacitor is electrically connected to the sixth line; the third line is a power supply line; the sixth line is a power supply line; the light emitting element comprises: a first electrode; a layer comprising an organic light emitting compound over the first electrode; and a second electrode over the layer; a luminescence from the organic light emitting compound is passed through the second electrode; and a ratio of a channel length to a channel width of the first transistor is different from a ratio of a channel length to a channel width of the third transistor.
 3. The light emitting device according to claim 2, wherein the other of the source and the drain of the second transistor is electrically connected to the third line.
 4. The light emitting device according to claim 2, wherein a gate of the third transistor is electrically connected to the third line.
 5. The light emitting device according to claim 2, wherein the semiconductor island forming the channel formation region of the second transistor and the channel formation region of the fourth transistor is a different semiconductor island from the semiconductor island forming the channel formation region of the first transistor and the channel formation region of the third transistor.
 6. The light emitting device according to claim 2, wherein the ratio of the channel length to the channel width of the third transistor is larger than the ratio of the channel length to the channel width of the first transistor.
 7. The light emitting device according to claim 2, wherein the third transistor is a driving transistor for driving the light emitting element.
 8. The light emitting device according to claim 2, wherein the third transistor is a depletion mode transistor for driving the light emitting element.
 9. The light emitting device according to claim 2, wherein the fourth transistor is a switching transistor.
 10. The light emitting device according to claim 2, wherein the first transistor is a current controlling transistor.
 11. The light emitting device according to claim 2, wherein the first transistor is an enhancement mode transistor.
 12. The light emitting device according to claim 2, wherein the first line is a scan line.
 13. The light emitting device according to claim 2, wherein the second line is a scan line.
 14. The light emitting device according to claim 2, wherein the fourth line is a signal line.
 15. The light emitting device according to claim 2, wherein the channel length of the first transistor is longer than the channel width of the first transistor.
 16. The light emitting device according to claim 2, wherein the first transistor has a P-type conductivity.
 17. The light emitting device according to claim 2, wherein the first transistor has an N-type conductivity.
 18. The light emitting device according to claim 2, wherein the light emitting element is formed over the third transistor.
 19. The light emitting device according to claim 2, wherein the fifth line is a signal line. 